1. Field of the Disclosure
Generally, the present disclosure relates to vertical capacitors, and, more specifically, to vertical capacitors with spaced conductive lines.
2. Description of the Related Art
Capacitors are employed in integrated circuit designs and other circuit designs to perform varied functions, such as memory access, signal bypassing and signal filtering. Typically, a capacitor includes two conductive plates separated by a layer of dielectric material. One problem with capacitors is that they typically require a relatively large physical region on the chip or board to obtain the desired capacitance.
One method for decreasing the physical area required for the capacitors includes stacking multiple layers of conductive plates together, each plate being one of a pair of oppositely polarized plates separated by an insulating material. However, such a method includes additional fabrication processing steps to realize the stack of plates, resulting in increased cost of manufacture. Another method for decreasing the physical area required for the capacitors includes forming layers of interlaced conductive lines separated by a dielectric material. Such a method allows for a higher capacitance than the stacked plates method given the same region.
FIGS. 1A and 1B are top views of a first metal layer 100 and a second metal layer 101 of an illustrative prior art capacitor arrangement. As shown in FIG. 1A, the first metal layer 100 includes two frames 110, 115 and a plurality of conductive lines 120, 125 spaced horizontally (on the same layer). Half of the conductive lines 120 are coupled to the top frame 110 while the other half of the conductive lines 125 are coupled to the bottom frame 115. The conductive lines 120, 125 are interlaced such that the conductive lines 120 coupled to the top frame 110 are separated by the conductive lines 125 coupled to the bottom frame 115. A dielectric material 150 separates the conductive lines 120, 125. The dielectric material 150 may be layers of silicon dioxide or other insulating dielectric materials to prevent unwanted electric shorts between layers. Different dielectric materials may be present in combination in various embodiments.
As shown in FIG. 1B, the second metal layer 101 includes two frames 130, 135 and a plurality of conductive lines 140, 145. Half of the conductive lines 140 are coupled to the right frame 130 while the other half of the conductive lines 145 are coupled to the left frame 135. The conductive lines 140, 145 are interlaced such that the conductive lines 140 coupled to the right frame 130 are separated by the conductive lines 145 coupled to the left frame 135. The dielectric material 150 separates the conductive lines 140, 145. Different dielectric materials may be present in combination in various embodiments.
As shown in FIG. 1C, the second metal layer 101 is positioned vertically above the first metal layer 100. The two metal layers 100, 101 are illustrated as partially transparent for clarity, and the frames 110, 115, 130, 135 may be coupled by one or more buses (not shown). The conductive lines 120, 125 of the first metal layer 100 are perpendicular to, i.e. oriented in an orthogonal direction to, the conductive lines 140, 145 of the second metal layer 101. Similarly, a subsequent metal layer (a third metal layer, not shown for clarity) would include conductive lines perpendicular to the second metal layer 101, and a fourth metal layer (not shown for clarity) would include conductive lines perpendicular to the third metal layer as illustrated in the partial cross-section of FIG. 2.
FIG. 2 illustrates a partial cross-sectional view of the layers 100 (M1) and 101 (M2) with additional layers M3 and M4. The M3 layer is substantially similar to the M1 layer while the M4 layer is substantially similar to the M2 layer. The cross-section does not include the frames of the various layers nor every conductive line of each layer. Multiple conductive lines 120, 125 from the first metal layer M1 are visible, but only one conductive line 145 from the second metal layer M2 is visible because the conductive lines from the different layers are perpendicular. Similarly, multiple conductive lines from the third layer M3 are visible, but only one conductive line from the fourth layer M4 is visible. The layers M1, M2, M3 and M4 are separated by the dielectric material 150, as is each individual conductive wire within the same layer. Different dielectric materials may be present in combination in various embodiments.
As the distance between metal layers M1, M2, M3 and M4 decreases, the dielectric material 150 may break down, thereby leading to undesirable electrical shorts and a reduction in the desired capacitance of the overall capacitor structure. The present disclosure is directed to a novel arrangement of spaced conductive lines within the capacitor that may eliminate or at least delay such unwanted dielectric breakdown, while at the same time allowing the conductive lines to be positioned closer together, thus increasing the capacitance in a given physical area.